RapidIO® 4.x BRC1 LP-Serial Streaming Endpoint Core
Features
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Implements a complete RapidIO Endpoint
solution for streaming data. -
Compliant with Rev. 4.1 of the specification.
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Implements RapidIO Error Management Extensions.
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Supports 1x, 2x, and 4x link widths at BRC1
data rates. -
Supports the High Availability/Redundant System
Hardware (HARSH) profiles. -
Supports the MECS Time Synchronization
Protocol. -
AXI4-Stream interfaces for sensor data.
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Management Entity with integrated decoder
for RapidIO maintenance transactions. -
IP-XACT support for rapid integration.
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Available for the following AMD and Intel FPGA families:
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AMD Versal
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Intel Agilex 7
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Intel Agilex 5
-
-
Porting kit is available for ASIC targets.
Description
The BRC1 LP-Serial Streaming Endpoint Core implements a complete RapidIO endpoint core capable of supporting link rates of up to 5.0 Gbps per lane. It includes functions that allow the endpoint to be managed with or without a local processor. Figure 1 illustrates the overall architecture of the core.
The core integrates a streaming sink block that maps
AXI4-Stream transactions into RapidIO Type 9 request
packets. The streaming source block maps RapidIO
Type 9 request packets to AXI4-Stream transactions.
The HARSH profile support provide a range of
features that support the creation of high availability
systems. This includes MECS timestamp synchronization
that coordinates timing functions across the system
with nano-second accuracy. The error management
functions provide detailed traceability of system level
errors along with optional error timestamping to assist
with error analysis.
RapidIO® 4.x BRC1 LP-Serial Streaming Endpoint Core