RapidIO® SwitchKit^TM

• From two to thirty two RapidIO ports, any mix of: LP-LVDS or LP-Serial physical layer ports.
• Physical layer ports are compliant with Rev. 1.2 of the specification.
• Supports RapidIO large or small transport model.
• Multicast port group support.
• Aggregate port group support for trunking and load balancing applications.
• Separate traffic queues for each port, and priority with separate traffic queues for unicast and multicast traffic.
• Supports RapidIO Error Management Extensions
• Optional Error Detection And Correction (EDAC) on all memory structures.

The switch provides wire-speed, non-blocking connectivity between RapidIO physical layer ports. The Switch Management Block handles maintenance transaction accesses to internal registers, as well as generating event notification messages.

Figure 1 illustrates the overall architecture of the switch.

RapidIO Physical Layer 8/16 LP-LVDS Specification
RapidIO 1x/4x LP-Serial Physical Layer Specification
RapidIO Common Transport Specification
RapidIO Error Management Extensions Specification
RapidIO Multicast Extensions Specification

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