RapidIO® I/O Logical Layer Target Core

• Compliant with Rev. 1.3 of the Input/Output Logical Layer specification.
• 32-bit AHB interface compliant with Rev. 2.0 AMBA standard.
• Seamless interface to Praesum’s LP-LVDS and LP-Serial physical layer cores.
• Available either as optimized FPGA netlists, or Verilog RTL source.

The I/O Layer Target Core converts RapidIO Input/Output Logical Layer transactions into AMBA AHB bus transactions. It gives remote endpoints direct, transparent access to AHB memory and peripheral devices across a RapidIO switch fabric.

Like all Praesum RapidIO IP solutions, it has been partitioned to support the Praesum fine-grained RapidIO IP architecture. This ensures that only the RapidIO functions needed for each application must be included. This saves valuable power and device resources in SOC ASIC or FPGA platforms.

Figure 1 illustrates the overall architecture of the core.

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