RapidIO® I/O Logical Layer Initiator Core

• Compliant with Rev. 2.1 of the Input/Output Logical Specification.
• Supports Error Management Extensions.
• Supports 8-bit and 16-bit deviceID formats.
• Supports 34-bit physical addressing.
• Supports NWRITE, NWRITE_R, SWRITE, and NREAD transactions.
• Architecturally neutral Bus Interface Unit Interface supports user defined Bus Interface Unit (BIU).
• Includes Verilog source code for reference BIU that implements OpenCores WISHBONE master interface.
• Seamless interface to Praesum’s LP-Serial Physical Layer Endpoint core.
• Available either as optimized FPGA netlists, or Verilog RTL source.

The I/O Layer Initiator Core encodes RapidIO IO Logical request packets, and decodes response packets. The core accepts write data from and returns read data to an external Bus Interface Unit (BIU) via an architecturally neutral interface.

The core includes a reference BIU that implements a WISHBONE slave interface. This interface can be connected directly to the LatticeMico32 Slave Passthrough module.

Like all Praesum RapidIO IP solutions, it has been partitioned to support the Praesum fine-grained RapidIO IP architecture. This ensures that only the RapidIO functions needed for each application must be included. This saves valuable power and device resources in SOC ASIC or FPGA platforms.

Figure 1 illustrates the overall architecture of the core.

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