FOR IMMEDIATE RELEASE
Preasum Communications, Inc. announced today availability of a new RapidIO IO Logical Layer Initiator Intellectual (IP) Property core. This core, when combined with Praesum’s RapidIO Physical Layer core, represents a complete solution for creating RapidIO processors. The solution has been demonstrated in a Xilinx Virtex-II Pro FPGA resulting the world’s first RapidIO processor.
The Logical Layer Core
The IO Logical Layer Initiator core serves as a bridge between the CoreConnect Processor Local Bus (PLB) and the RapidIO Physical Layer. It translates PLB bus transactions into Logical Layer packets for transport over RapidIO. The core directly interfaces to any processor core that supports the IBM CoreConnect architecture.
The core is licensed as Verilog source and includes a testbench as well as an interface to the Motorola RapidIO verification testsuite. The core is priced at $50,000 and is available now. A companion IO Logical Layer target core will be available in August.
Demonstrated at the System Level In FPGA Technology
The core has been demonstrated at the system level using Xilinx Virtex-II Pro FPGAs. This is in addition to demonstrated interoperability with the Motorola RapidIO Bus Functional Model (BFM).
"The use of FPGA technology let us verify the complete solution interacting with a PowerPC 405 core across the CoreConnect PLB bus at speed," said Kent Dahlgren, President of Praesum Communications. "Our FPGA based evaluation platform will also allow us to demonstrate interoperability with other RapidIO products as they become available."
About Praesum Communications
Praesum Communications is the RapidIO solutions leader. Our Serial RapidIO Endpoint and Switching IP enable next generation systems. Founded in January 2000, Praesum has its headquarters in Petaluma, CA. For more information, visit the Praesum web site at www.praesum.com.
Product Marketing Contact:
Praesum Communications, Inc.
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